RTL Design - Lead Engineer Relevant Experience: 4 to 12 years Job Description: - Strong knowledge in IP/SOC design methodologies. - Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows - Good experience in Synthesis - Good communication skills to work in a cross functional international team digital and software design engineers - The design engineer should architect digital subsystem together with system designer - IP development and coding using standard coding guide lines - Basic synthesis knowledge & timing required - Must have strong knowledge of AMBA AHB/AXI protocol - Working knowledge on code coverage, functional coverage, Lint, CDC etc - Low power design Job Type: Full-time Salary: ₹800,000.00 - ₹3,500,000.00 per year Experience: - work: 1 year (Preferred) - total work: 1 year (Preferred) Education: - Bachelor's (Preferred) Work Remotely: - Temporarily due to COVID-19 COVID-19 Precaution(s): - Remote interview process - Virtual meeting

RTL Design - Lead Engineer Relevant Experience: 4 to 12 years Job Description: - Strong knowledge in IP/SOC design methodologies. - Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows - Good experience in Synthesis - Good communication skills to work in a cross functional international team digital and software design engineers - The design engineer should architect digital subsystem together with system designer - IP development and coding using standard coding guide lines - Basic synthesis knowledge & timing required - Must have strong knowledge of AMBA AHB/AXI protocol - Working knowledge on code coverage, functional coverage, Lint, CDC etc - Low power design Job Type: Full-time Salary: ₹800,000.00 - ₹3,500,000.00 per year Experience: - work: 1 year (Preferred) - total work: 1 year (Preferred) Education: - Bachelor's (Preferred) Work Remotely: - Temporarily due to COVID-19 COVID-19 Precaution(s): - Remote interview process - Virtual meeting

RTL Design - Lead Engineer Relevant Experience: 4 to 12 years Job Description: - Strong knowledge in IP/SOC design methodologies. - Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows - Good experience in Synthesis - Good communication skills to work in a cross functional international team digital and software design engineers - The design engineer should architect digital subsystem together with system designer - IP development and coding using standard coding guide lines - Basic synthesis knowledge & timing required - Must have strong knowledge of AMBA AHB/AXI protocol - Working knowledge on code coverage, functional coverage, Lint, CDC etc - Low power design Job Type: Full-time Salary: ₹800,000.00 - ₹3,500,000.00 per year Experience: - work: 1 year (Preferred) - total work: 1 year (Preferred) Education: - Bachelor's (Preferred) Work Remotely: - Temporarily due to COVID-19 COVID-19 Precaution(s): - Remote interview process - Virtual meeting

RTL Design - Lead Engineer Relevant Experience: 4 to 12 years Job Description: - Strong knowledge in IP/SOC design methodologies. - Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows - Good experience in Synthesis - Good communication skills to work in a cross functional international team digital and software design engineers - The design engineer should architect digital subsystem together with system designer - IP development and coding using standard coding guide lines - Basic synthesis knowledge & timing required - Must have strong knowledge of AMBA AHB/AXI protocol - Working knowledge on code coverage, functional coverage, Lint, CDC etc - Low power design Job Type: Full-time Salary: ₹800,000.00 - ₹3,500,000.00 per year Experience: - work: 1 year (Preferred) - total work: 1 year (Preferred) Education: - Bachelor's (Preferred) Work Remotely: - Temporarily due to COVID-19 COVID-19 Precaution(s): - Remote interview process - Virtual meeting

RTL Design - Lead Engineer Relevant Experience: 4 to 12 years Job Description: - Strong knowledge in IP/SOC design methodologies. - Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows - Good experience in Synthesis - Good communication skills to work in a cross functional international team digital and software design engineers - The design engineer should architect digital subsystem together with system designer - IP development and coding using standard coding guide lines - Basic synthesis knowledge & timing required - Must have strong knowledge of AMBA AHB/AXI protocol - Working knowledge on code coverage, functional coverage, Lint, CDC etc - Low power design Job Type: Full-time Salary: ₹800,000.00 - ₹3,500,000.00 per year Experience: - work: 1 year (Preferred) - total work: 1 year (Preferred) Education: - Bachelor's (Preferred) Work Remotely: - Temporarily due to COVID-19 COVID-19 Precaution(s): - Remote interview process - Virtual meeting

RTL Design - Lead Engineer Relevant Experience: 4 to 12 years Job Description: - Strong knowledge in IP/SOC design methodologies. - Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows - Good experience in Synthesis - Good communication skills to work in a cross functional international team digital and software design engineers - The design engineer should architect digital subsystem together with system designer - IP development and coding using standard coding guide lines - Basic synthesis knowledge & timing required - Must have strong knowledge of AMBA AHB/AXI protocol - Working knowledge on code coverage, functional coverage, Lint, CDC etc - Low power design Job Type: Full-time Salary: ₹800,000.00 - ₹3,500,000.00 per year Experience: - work: 1 year (Preferred) - total work: 1 year (Preferred) Education: - Bachelor's (Preferred) Work Remotely: - Temporarily due to COVID-19 COVID-19 Precaution(s): - Remote interview process - Virtual meeting

Date: 19-Jan-2021 Location: Bangalore Company: LTTS Experience 4 -8 Years Technical Focus Areas - Good understanding of Multi-processor and cache designs Hands on coding experience in Verilog/VHDL - Familiarity with various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols - Has good knowledge on various tools viz Spyglass, 0-in,LEC etc - Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus The original job offer can be found in Kit Job: www.kitjob.in/job/20835988/umf02-rtl-designer-bangalore-rural/

Date: 19-Jan-2021 Location: Bangalore Company: LTTS Experience 4 -8 Years Technical Focus Areas - Good understanding of Multi-processor and cache designs Hands on coding experience in Verilog/VHDL - Familiarity with various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols - Has good knowledge on various tools viz Spyglass, 0-in,LEC etc - Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus The original job offer can be found in Kit Job: www.kitjob.in/job/20835988/umf02-rtl-designer-bangalore-rural/

RTL designer Date: 19-Jan-2021 Location: Bangalore Company: LTTS Experience 4 -8 Years Technical Focus Areas - Good understanding of Multi-processor and cache designs Hands on coding experience in Verilog/VHDL - Familiarity with various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols - Has good knowledge on various tools viz Spyglass, 0-in,LEC etc - Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus The original job offer can be found in Kit Job: www.kitjob.in/job/20838377/r-397-rtl-designer-bangalore-rural/

Date: 19-Jan-2021 Location: Bangalore Company: LTTS Experience 4 -8 Years Technical Focus Areas - Good understanding of Multi-processor and cache designs Hands on coding experience in Verilog/VHDL - Familiarity with various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols - Has good knowledge on various tools viz Spyglass, 0-in,LEC etc - Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus The original job offer can be found in Kit Job: www.kitjob.in/job/20835988/umf02-rtl-designer-bangalore-rural/

Job Description Technical Focus Areas Good understanding of Multi-processor and cache designs Hands on coding experience in Verilog/VHDL Familiarity with various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols Has good knowledge on various tools viz Spyglass, 0-in,LEC etc Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus Job Function: IT Hardware:Hardware Products & ServicesIndustry:IT-Hardware/Networking, TelecomSpecialization:Hardware Design Qualification: Any GraduateEmployment Type: Full Time

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering Job Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Job Description Job Description: - 8 to 10 years of work experience in ASIC/SoC Design - Experience in Logic design /micro-architecture / RTL coding is a must - Must have hands on experience with SoC design and integration for complex SoCs - Experience in Verilog/System-Verilog is a must. - Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC - Understanding of

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering Job Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Job Description Job Description: - 8 to 10 years of work experience in ASIC/SoC Design - Experience in Logic design /micro-architecture / RTL coding is a must - Must have hands on experience with SoC design and integration for complex SoCs - Experience in Verilog/System-Verilog is a must. - Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC - Understanding of

# 1. RTL Design - Lead Engineer Relevant Experience:4 to 12 yearsJob Description:Strong knowledge in IP/SOC design methodologies.Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flowsGood experience in SynthesisGood communication skills to work in a cross functional international team digital and software design engineersThe design engineer should architect digital subsystem together with system designerIP development and coding using standard coding guide linesBasic synthesis knowledge & timing requiredMust have strong knowledge of AMBA AHB/AXI protocolWorking knowledge on code coverage, functional coverage, Lint, CDC etcLow power designJob Type:Full-timeSalary:?700,000.00 - ?3,500,000.00 per yearSchedule:Morning shiftExperience:total work:3 years (Preferred)Education:Bachelor's (Required)

# 1. RTL Design - Lead Engineer Relevant Experience: 4 to 12 years Job Description: - Strong knowledge in IP/SOC design methodologies. - Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows - Good experience in Synthesis - Good communication skills to work in a cross functional international team digital and software design engineers - The design engineer should architect digital subsystem together with system designer - IP development and coding using standard coding guide lines - Basic synthesis knowledge & timing required - Must have strong knowledge of AMBA AHB/AXI protocol - Working knowledge on code coverage, functional coverage, Lint, CDC etc - Low power design Job Type: Full-time Salary: ₹700,000.00 - ₹3,500,000.00 per year Schedule: - Morning shift Experience: - total work: 3 years (Preferred) Education: - Bachelor's (Required) The original job offer can be found in Kit Job: www.kitjob.in/job/19873419/rtl-designer-gff-104-bangalo

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