Work Location: Greater Noida The position is an exciting opportunity to be part of a flexible and dynamic team in the growing markets of mixed signal chips with signal processing IPs, ARM processor and AMBA bus interface like Wireless Chargers, Bluetooth, PMIC etc. used in Mobile, Tablets, Microcontrollers etc. The role works within the digital verification team in Greater Noida collaborating with the design and verification teams in Italy and Singapore creating SV UVM based verification environment, using various apps of JasperGold to ensure design quality and qualify the testbench using Certitude. Job scope: Work on IP verification or SOC verification. Verification planning using v-plan, functional points identification, and review. SV UVM based test-bench development. Implementation using different verification techniques (constraint random dynamics simulation and static formal verification). Verification closure by ensuring 100% code and functional coverage. Schedule preparation a

Job De ion:8 - 12 years experience in Design VerificationExpert Knowledge in IP VerificationVery strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interfaceMust have expert knowledge in coverage driven test planningMust have expert knowledge in architecting configurable environmentsMust have very strong System Verilog and UVM backgroundMust be able to lead the team technically in all aspects, must be able to drive multiple projectsPast experience leading and managing teams highly desiredExcellent Communication and Presentation SkillsAbility and desire to learn new methodologies, languages, protocols etc. is requiredWafer Space is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading

We're immediately hiring for Verification EngineerRole: Verification EngineerLocation: HyderabadExperience: 2-4 yearsJob description:- BS/MS in ECE with 2-4 years of experience in FPGA IP's/System/Co-simulations- Proficiency in Verilog, System Verilog, C and any scripting language (tcl/perl/python)- Experience in High speed bus interfaces (PCIe/Ethernet/USB) and high bandwidth memory Verification- Experience in Xilinx Vivado based system/Co-simulation flows- AMBA AXI, PCIe protocol and Cache expertise is a plus- Good documentation and presentation skills- Good communication (Verbal and written) and teamwork skillsAbout Company:Infometry Inc is a pure play Business intelligence company, located in Bay Area( Fremont, CA). Also, have offshore locations in Bangalore and Singapore. We are leading Data Analytics company, Certified Engineering, Implementation partner for Informatica, Tableau, Snowflake, Matillion, Talend, Google Cloud (GCP), Dell Boomi, Adaptive Insights, CallidusCloud

We're immediately hiring for Validation EngineerRole: Validation EngineerLocation: HyderabadExperience: 2-4 yearsJob description:- BS/MS in ECE with 2-4 years of experience in FPGA/Silicon Validation- Proficiency in C, Verilog and any scripting language (tcl/perl/python)- Experience in High speed bus interfaces (PCIe/Ethernet/USB) and high bandwidth memory Validation- Experience in Xilinx Vivado/ISE tool knowledge and understanding of timing and implementation reports- Debug expertise with Xilinx Chipscope (ILA) and protocol analyzers (Lecroy)- AMBA AXI, PCIe bus protocol and Cache expertise is a plus- Good documentation and presentation skills- Good communication (Verbal and written) and teamwork skillsAbout Company:Infometry Inc is a pure play Business intelligence company, located in Bay Area( Fremont, CA). Also, have offshore locations in Bangalore and Singapore. We are leading Data Analytics company, Certified Engineering, Implementation partner for Informatica, Tableau, Snow

Dear Applicant, This position Software Engineer II is for one of the World's leading developer of Electronic Design Automation (EDA) Products & Services And Is a Fortune 100 organisation. The Place Of Posting is for its Ahmedabad, Gujarat location. Minimum Experience level: 2+ years Education: BE/ B.Tech/ ME / M.Tech / MS Electronics and communications. Requirements: - B.E./B.Tech./M.E./M.Tech. degree with relevant 3+ years of experience. - Good working knowledge of various verification concepts such as Verification architecture, coverage, checkers, test plan etc. - Strong in building Verification environments based on UVM, System Verilog - Strong analytical and problem-solving skills with an ability to visualize processes and outcomes. - Outstanding all-round communication skills and ability to work collaboratively in a dynamic multi-location environment. Strong Plus: - Domain expertise in AMBA Protocol knowledge - Programming skills: C, C+ Note - The Client prefers local candidat

We are hiring a content writer for the technology or eCommerce websites Skills Required - English Writing & Basic Computer Knowledge Qualification - 12th Pass or Above You will learn here SEO basic, On-page and Off-page SEO tactics, social media, email marketing, and other different areas of digital marketing. You have a great opportunity to learn about digital marketing. We also provide a stipend that will depend on your skills and interview Company address - 304, Amba Tower, 3rd Floor, DC Chowk, Sector 9, Rohini, Delhi, 110085 Call us today for an interview - 7379787463

ASIC/SOC Design Technical Manager/Manager/Lead: -ASIC integration, peripherals, Bus Design, ASIC Design, RTL Design, DC/PC, LINT, PTSI, Verilog/VHDL) -Timing Constraints & Closure (PTSI, STA, Primetime) -RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency) -Multimedia/Camera Imaging (Image processing algorithms, ASIC Design, RTL Coding, JPEG, C/C+/SystemC, Modelsim, Synopsys DC, LEC, Spyglass) -Low Power Design (clock gating, power gating, power grids, power integrity) -IC Design Methodology (Design Methodology, Simulation Tools, Performance Modeling, Architecture to GDSII) -Interconnect Architect & Design (ASIC Design, Bus Protocols, AHB, AXI, NoC, Architecture Tradeoff Analysis, Micro-Architecture, CPU Architecture) -DDR & Cache System Micro-Architect (ASIC Design, Performance Bottleneck Analysis for interconnects & memory controller, Bus Protocols: AMBA AXI, CoreConnect, O

Responsibilities br&gtbr&gt Understand Standard Specifications the functional specifications feature enhancements for the product and create microarchitecture and detailed design documents for some of the components of the design with medium complexity.br&gtbr&gt Be an individual contributor in the Design Tasks RTL coding of design, debug, verification coverage improvement in the directed Verilog Test Bench, etc.br&gtbr&gt Create work on designs using Low Power Design Methodology and automotive safetybr&gtbr&gt May need to understand Standard Specifications the functional specifications feature enhancements for the product and create microarchitecture and detailed design documents for some of the components of small complexity functions product features for the DesignWare family of synthesizable cores in protocol areas such as AMBA \(AMBA2, AXI, CHI\) SDeMMCDDRPCIeEthernet USB MIPIbr&gtbr&gt Creates deliverables which do not require close review

Job ProfileCompany:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware EngineeringJob Overview:Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. IT takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.Job Description:8 to years of work experience in ASIC/SoC DesignExperience in Logic design /micro-architecture / RTL coding is a mustMust have hands on experience with SoC design and integration for complex SoCsExperience in Verilog/System-Verilog is a must.Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCCUnderstanding of Memory controller designs and m

Worked on SoC/IP level testbench and verification Hands-on with SV and Assertion-based verification methodology. At least 2 years of experience on HVL (SV, Verilog, Specman, E, VMM, OVM, UVM) Worked on AMBA, USB, DDR, PCIE, ethernet Call 9870322453 The original job offer can be found in Kit Job: www.kitjob.in/job/21143015/tek446-soc-verification-engineer-noida/

Digital Hikes is hiring fresher candidates for SEO.Basic computer knowledge & English requiredAddress \- 304, Amba Tower, 3rd Floor, DC Chowk, Sector 9, Rohini, Delhi, 110085Phone Number \- 7379787463Salary based on your interview & skills

Digital Hikes is hiring fresher candidates for SEO.Basic computer knowledge & English requiredAddress - 304, Amba Tower, 3rd Floor, DC Chowk, Sector 9, Rohini, Delhi, 110085Phone Number - 7379787463Salary based on your interview & skills

Job Description The position is an exciting opportunity to be part of a flexible and dynamic team in the growing markets of mixed signal chips with signal processing IPs, ARM processor and AMBA bus interface like Wireless Chargers, Bluetooth, PMIC etc. used in Mobile, Tablets, Microcontrollers etc. The role works within the digital verification team in Greater Noida collaborating with the design and verification teams in Italy and Singapore creating SV UVM based verification environment, using various apps of JasperGold to ensure design quality and qualify the testbench using Certitude. Job scope: Work on IP verification or SOC verification. Verification planning using v-plan, functional points identification, and review. SV UVM based test-bench development. Implementation using different verification techniques (constraint random dynamics simulation and static formal verification). Verification closure by ensuring 100 PERCENT code and functional coverage. Schedule preparation and exec

Experience- 0-2 yrs Location- Rohini, Delhi Designation- SEO Executive, Content Writer Job Description Fresher Candidate - Fresher Candidates are welcomed to walk in Interview. Candidate must know about BASIC OF COMPUTER & Flexible to WRITE CONTENT IN ENGLISH. For SEO Experienced Candidate - The candidate must know about the On Page & Off Page Tactics, And previously have done the White Hat SEO practice on live projects. On Page Skills - Content Optimization, Keywords Research, Webmaster, Content Creation Off Page Skills - Blog Posting, Backlink Creation, PDF Submission, PPT Submission, Article Submission Note: Interview outcome will be based on your ENGLISH WRITING SKILLS. Industry Type IT Company, Affiliate Marketing, Training Employer Details Company Name - Digitalhikes Company Website- www.digitalhikes.com Contact Person- Vijay Bihani Address- Digitalhikes Amba Tower, 3rd Floor DC Chowk, Rohini Sec-9 Delhi Expected Start Date: 15/2/2021 Job Type: Full-time Salary: ₹8,000.00

Responsibilities:- Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of the design with medium complexity.- Be an individual contributor in the Design Tasks - RTL coding of design, debug, verification coverage improvement in the directed Verilog Test Bench, etc.- Create/ work on designs using Low Power Design Methodology and automotive safety- May need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity functions/ product features for the DesignWare family of synthesizable cores in protocol areas such as AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/Ethernet/ USB/ MIPI- Creates deliverables which do not require close review or supervision by a Senior Technical Lead.- May learn to do technical

Advertisements